ASIC System Level Test Engineer, PhD, University Graduate

Develop System Level Test (SLT) solutions for custom Application-Specific Integrated Circuits (ASIC) and SoC’s by specifying hardware and integration requirements, driving vendor interactions, developing software frameworks and test modules, and integrating test cases from silicon validation and system software and test teams.

Partner with data center server and accelerator design teams to realize practical test solutions leveraging system design and test elements.

Partner with hardware and software teams to evaluate functional device yield and performance across various operating conditions, characterize hardware/software interaction, and develop effective production screens to reduce defective parts per million.

Integrate test software and hardware solutions with robotic chip handlers, drive bring-up of the fully integrated solution in internal and partner NPI labs, transfer all collaterals needed for HVM at Offshore Assembly and Test (OSAT) facilities, and provide ongoing HVM support.

PhD degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.

Academic, educational, internship, or project experience with product engineering, test engineering, hardware validation, silicon validation.

Experience with Python programming or Linux/Unix.