About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

In this role, you will be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You will work with multi-disciplinary teams throughout custom silicon development, focusing on substrate technology, design tradeoffs, assembly evaluation, and mechanical reliability. As an advanced packaging technologist, you will develop advanced packaging solutions (2.5D/3D/3.5D) for ML chips. This involves collaborating with architects, SI/PI, thermal, and PCB engineers to create high-performance packages optimized for electrical performance, reliability, and assembly.

You will be instrumental in identifying and incorporating advanced packaging technologies into Google chip designs. Your work spans from circuit design to large-scale system design, seeing products through to high-volume manufacturing, which directly influences our data centers and impacts Google users.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Develop next-generation packaging breakthroughs and qualify high-performance foundry solutions.

• Drive the development of advanced test macro features and execute engineering plans for next-generation package architectures.

• Identify packaging risks and document technical assessments to guide the definition of critical test vehicles.

• Define and implement robust DFx (DFM, DFR, DFT) methodologies tailored specifically for advanced packaging technologies.

• Collaborate with internal teams, foundries, OSATs, and suppliers to deliver production-ready chip package solutions through execution of shared engineering plans.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

• 5 years of experience with package development for high volume production.

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.

• Experience with co-packaged copper (CPC), co-packaged optics (CPO), and silicon photonics.

• Experience in developing new technologies and driving innovation within the semiconductor packaging space.

• Experience working directly within wafer foundries or assembly houses (OSATs).

• Knowledge of 2.5D and 3D failure modes and reliability standards.

• In-depth understanding of the interactions between packaging technology, electrical design, thermal/mechanical performance, and manufacturability.