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职位Google

Senior Board Design Engineer

Google

Senior Board Design Engineer

Google

·

On-site

·

Full-time

·

2w ago

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a Hardware Board Design Engineer, you will own the electrical design of complex High Performance Computing (HPC) systems. You will drive the development of next-generation AI accelerator boards, ensuring they meet signal integrity, power delivery, and thermal requirements. You will work cross-functionally with Silicon (ASIC), Signal Integrity, Power, Mechanical, and Manufacturing teams to bring products from concept to mass production.

The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

Responsibilities

  • Lead the schematic capture and component selection for high-density, multi-layer Printed Circuit Boards (20+ layers) incorporating high-power ASICs (TPUs/CPUs), FPGAs, and high-speed memory (High Bandwidth Memory/DDR5).

  • Design and validate high-speed interfaces including Peripheral Component Interconnect Express (PCIe) Gen 6.0/7.0, 400G/800G/1.6T ethernet (PAM4). Collaborate with Signal Integrity (SI) engineers to define routing constraints and stack-up.

  • Design multi-phase power regulators (VRMs) capable of delivering 1000A currents with fast transient response for AI processors.

  • Work closely with PCB layout designers to guide placement and routing of critical signals and power planes.

  • Lead the lab bring-up of first-silicon/first-board. Debug complex hardware issues using oscilloscopes, Time-Domain Reflectometers (TDRs), and logic analyzers. Root-cause failures to component, assembly, or design issues

Minimum qualifications

  • Bachelor's degree in Electrical Engineering, or equivalent practical experience.

  • 5 years of experience in board design (schematic and layout supervision) for server, networking, or high performance computing products.

  • Experience in designing with serial interfaces (e.g., Ser Des, PCIe, Ethernet, DDR) and signal integrity (insertion loss, crosstalk, impedance matching).

Preferred qualifications

  • Experience with DC-DC power converter design and power integrity concepts.

  • Experience bringing up complex So Cs and debugging interaction between hardware, firmware, and software.

  • Proficiency with Electronic Design Automation (EDA) tools (Cadence Concept/Allegro, or similar).

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关于Google

Google

Google

Public

Google specializes in internet-related services and products, including search, advertising, and software.

10,001+

员工数

Mountain View

总部位置

$1,700B

企业估值

评价

3.7

25条评价

工作生活平衡

3.8

薪酬

4.2

企业文化

3.4

职业发展

3.9

管理层

2.8

68%

推荐给朋友

优点

Excellent compensation and benefits

Smart and talented colleagues

Great perks and work flexibility

缺点

Management and leadership issues

Bureaucracy and slow processes

Constantly changing priorities and reorganizations

薪资范围

57,502个数据点

Junior/L3

L3

L4

L5

L6

L7

L8

Mid/L4

Principal/L7

Senior/L5

Staff/L6

Director

Junior/L3 · Data Scientist L3

0份报告

$176,704

年薪总额

基本工资

-

股票

-

奖金

-

$150,298

$203,110

面试经验

9次面试

难度

3.4

/ 5

时长

14-28周

录用率

44%

体验

正面 0%

中性 56%

负面 44%

面试流程

1

Application Review

2

Online Assessment/Technical Screen

3

Phone Screen

4

Onsite/Virtual Interviews

5

Team Matching

6

Offer

常见问题

Coding/Algorithm

System Design

Behavioral/STAR

Technical Knowledge

Product Sense