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About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Hardware Board Design Engineer, you will own the electrical design of complex High Performance Computing (HPC) systems. You will drive the development of next-generation AI accelerator boards, ensuring they meet signal integrity, power delivery, and thermal requirements. You will work cross-functionally with Silicon (ASIC), Signal Integrity, Power, Mechanical, and Manufacturing teams to bring products from concept to mass production.
The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
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Lead the schematic capture and component selection for high-density, multi-layer Printed Circuit Boards (20+ layers) incorporating high-power ASICs (TPUs/CPUs), FPGAs, and high-speed memory (High Bandwidth Memory/DDR5).
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Design and validate high-speed interfaces including Peripheral Component Interconnect Express (PCIe) Gen 6.0/7.0, 400G/800G/1.6T ethernet (PAM4). Collaborate with Signal Integrity (SI) engineers to define routing constraints and stack-up.
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Design multi-phase power regulators (VRMs) capable of delivering 1000A currents with fast transient response for AI processors.
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Work closely with PCB layout designers to guide placement and routing of critical signals and power planes.
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Lead the lab bring-up of first-silicon/first-board. Debug complex hardware issues using oscilloscopes, Time-Domain Reflectometers (TDRs), and logic analyzers. Root-cause failures to component, assembly, or design issues
Minimum qualifications
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Bachelor's degree in Electrical Engineering, or equivalent practical experience.
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5 years of experience in board design (schematic and layout supervision) for server, networking, or high performance computing products.
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Experience in designing with serial interfaces (e.g., Ser Des, PCIe, Ethernet, DDR) and signal integrity (insertion loss, crosstalk, impedance matching).
Preferred qualifications
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Experience with DC-DC power converter design and power integrity concepts.
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Experience bringing up complex So Cs and debugging interaction between hardware, firmware, and software.
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Proficiency with Electronic Design Automation (EDA) tools (Cadence Concept/Allegro, or similar).
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Googleについて

Google specializes in internet-related services and products, including search, advertising, and software.
10,001+
従業員数
Mountain View
本社所在地
$1,700B
企業価値
レビュー
3.7
25件のレビュー
ワークライフバランス
3.8
報酬
4.2
企業文化
3.4
キャリア
3.9
経営陣
2.8
68%
友人に勧める
良い点
Excellent compensation and benefits
Smart and talented colleagues
Great perks and work flexibility
改善点
Management and leadership issues
Bureaucracy and slow processes
Constantly changing priorities and reorganizations
給与レンジ
57,502件のデータ
Junior/L3
L3
L4
L5
L6
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L8
Mid/L4
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Director
Junior/L3 · Data Scientist L3
0件のレポート
$176,704
年収総額
基本給
-
ストック
-
ボーナス
-
$150,298
$203,110
面接体験
9件の面接
難易度
3.4
/ 5
期間
14-28週間
内定率
44%
体験
ポジティブ 0%
普通 56%
ネガティブ 44%
面接プロセス
1
Application Review
2
Online Assessment/Technical Screen
3
Phone Screen
4
Onsite/Virtual Interviews
5
Team Matching
6
Offer
よくある質問
Coding/Algorithm
System Design
Behavioral/STAR
Technical Knowledge
Product Sense
ニュース&話題
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3d ago
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3d ago