About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will collaborate with software and hardware architects to explore Platform and Chassis trade-offs in Tensor SOC. You will develop and use analytical tools, simulation, emulation, and post-silicon measurements to perform holistic analysis of large complex ASIC designs. You will influence current and next generation SOCs in the product lineup, and play highly visible roles from ideation through mass production of our SOCs. As part of this work, you will participate in the development of exceptional technologies in fabric, memory, etc., and filing associated patents.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

• Impact and influence multiple stages of the SOC lifecycle, from ideation and concept through tapeout, bringup and mass production.

• Participate in architectural design and evaluation of future ASIC designs.

• Participate in creating architectural specifications for ASIC.

• Optimize top-level architectural definition to handle complex multi-IP flows. Communicate the analysis results in both qualitative and quantitative fashion.

• Develop modeling simulators and architectural models of various subsystems within an ASIC to evaluate interactive and novel workloads.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.

• 15 years of experience with silicon digital design/architecture.

• Experience with two or more of the following: CPU, GPU, ISP, display, video codecs, memory controllers, fabrics, compression, storage, one-time programmable memory (OTP), interrupts, interfaces, debugging/profiling mechanism, power management system.

Preferred qualifications

• Master’s degree or PhD in Computer Science, Electrical Engineering or a related field.

• 18 years of industry experience.

• Experience with processor core architectures (such as ARM, x86, RISC-V, etc.) and IPs commonly used in SoC designs.

• Experience analyzing multi-IP workload use cases, tools, and simulators at different abstraction levels (cycle accurate, TLM, or functional).

• Experience designing/implementing or validating RTL for CPU, GPU, fabric, memory, caches, camera, video, display, and access control elements.

• Knowledge of hardware performance monitors or profiling, power management and optimization, and with OS, firmware, software stack, OpenGL, OpenCL, Java, Codec.