Architect and implement next generation physical design EDA, and CAD tool workflows for ASIC development.

Collaborate with chip design teams to implement tools and methodologies for physical design in leading edge process nodes.

Develop auditing tools, checkers, and metric dashboards based on APIs from third-party EDA tools.

Own the physical design of blocks and subsystems end-to-end.

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

8 years of experience with physical design flow and methodologies.

Experience with EDA tools for physical design (e.g., Cadence, Synopsys, Siemens).

Experience in full-chip or block-level physical design.

Experience with scripting in Python, Tcl, or Perl.