Review chip specification and design, develop the integration plan with software and system partners, co-ordinate hardware and software delivery and demonstrate functionality.

Integrate and validate hardware and software designs, including first-party and third-party IPs, assist bringup of machine learning compute features, and develop firmware to help validate hardware functionality.

Utilize hardware/software co-simulation methodologies leveraging Register-Transfer Level (RTL) simulation, Emulation, FPGA environments as appropriate, architectural simulators or performance models as required to correlate performance.

Develop detailed test plans, based on design specifications coordinated with a cross-functional team (e.g., Design, Design Verification, Firmware, Compiler, Architecture).

Assist debug discussions with Design, Design Verification, Architecture teams and help root-cause functional failures and performance issues through the product development cycle, while improving validation coverage and sign-off processes for high-quality tapeout and production deployment.

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

2 years of experience in two or more of the following areas: computer architecture, embedded firmware, ASIC design or verification, integration and enablement of first-party or third-party IPs.

Experience in hardware/software integration or validation.

Experience with Register-Transfer Level (RTL) development, design verification, or evaluation.