Analyze and improve compiler quality, performance, optimization decisions, correctness and compilation time as part of the EdgeTPU compiler team.

Develop and enhance parallelization and scheduling algorithms to reduce compute and data movement costs for executing ML workloads on the EdgeTPU.

Collaborate with EdgeTPU architects to shape future accelerators, the Hardware/Software (HW/SW) interface, and co-optimizations of the next-generation EdgeTPU architectures.

Work on efficient mapping of generative AI models and other key workloads into EdgeTPU instructions through the compiler.

Bachelor’s degree or equivalent practical experience.

2 years of experience working with embedded systems or device software.

2 years of experience with compilers (development, parallelization, etc.).

2 years of experience with software development in one or more programming languages (e.g. C++), or 1 year of experience with an advanced degree.