About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will work as part of a research and development team. You will build verification components, constrained-random testing, system testing, and verification closure. You will verify digital designs, collaborate with design and verification engineers on projects, and perform direct verification. You will build constrained-random verification environments that exercise designs through their corner cases and expose all types of bugs. You will manage the full lifecycle of verification which can range from verification planning, test execution, or collecting and closing coverage.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Plan the verification of digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.

• Create and enhance constrained-random verification environments using System Verilog or formally verify designs with strategic value add (SVA) and industry-leading formal tools.

• Identify and write all types of coverage measures for stimulus and corner cases.

• Debug tests with design engineers to deliver functionally correct design blocks.

• Close coverage measures to identify verification holes and to show progress towards tape-out.

Minimum qualifications

• Bachelor's degree in electrical engineering or equivalent practical experience.

• 4 years of experience working with design networking like remote direct memory access (RDMA) or packet processing and system design principles for low latency, throughput, security, and reliability.

• Experience creating and using verification components and environments in standard verification methodology.

Preferred qualifications

• Experience in verifying digital systems using standard internet protocol (IP) components or interconnects (e.g., microprocessor cores, hierarchical memory subsystems).

• Experience in transmission control protocol (TCP), IP, ethernet, PCIE, and dynamic random-access memory (DRAM), network on chip (NoC) principles and protocols.

• Experience in estimating performance by analysis, modeling, and network simulation in defining and driving performance test plans.

• Experience with verification techniques and the full verification lifecycle.

• Experience with performance verification of ASICs and ASIC components.

• Experience with ASIC standard interfaces and memory system architecture.