Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.

Create and enhance constrained-random verification environments using System Verilog and UVM, or formally verify designs with SVA and industry leading formal tools.

Identify and write all types of coverage measures for stimulus and corner-cases.

Debug tests with design engineers to deliver functionally correct design blocks.

Close coverage measures to identify verification holes and to show progress towards tape-out.

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

4 years of experience with design verification.

Experience with System Verilog/Verilog.