Define custom silicon Application-Specific Integrated Circuit (ASIC) reliability specifications based on Joint Electron Device Engineering Council (JEDEC) standards and Google product field usage conditions.

Execute Application-Specific Integrated Circuit (ASIC) product reliability qualification tests, including High Temperature Operating Life (HTOL), Electrostatic Discharge (ESD), Latch-Up (LU), Early Life Failure Rate (ELFR), Temperature Cycling (TC), and Biased Highly Accelerated Stress Test (BHAST) testing.

Utilize statistical methods and failure analysis to estimate System-on-Chip (SOC) life times and evaluate Complementary Metal-Oxide-Semiconductor (CMOS) technology reliability.

Collaborate with cross-functional internal and external teams, such as Complementary Metal-Oxide-Semiconductor (CMOS) foundries, Outsourced Semiconductor Assembly and Tests (OSATs), and third-party qualification facilities.

Bachelor's degree in Electrical Engineering, Material Science, Mechanical Engineering, Physics, or a related technical field, or equivalent practical experience.

6 years of experience in logic Application-Specific Integrated Circuit (ASIC) device and package reliability Joint Electron Device Engineering Council (JEDEC) qualification, including High Temperature Operating Life (HTOL), Electrostatic Discharge (ESD), Latch-Up (LU), Temperature Cycling (TC), and Highly Accelerated Stress Test (HAST).

Experience in semiconductor device physics, transistor reliability, CMOS technology and manufacturing.