About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

In this role, you will help build the SoC’s that power these data centers by developing and deploying comprehensive test solutions with Automatic Test Equipment (ATE) for New Product Introduction (NPI) and for High Volume Manufacturing (HVM) at wafer fabs and OSATs. This is an opportunity to create silicon and follow it into the field to close the loop back to design and test for the next generations of chips.

You will be a key member of the team that drives System Level Test (SLT) manufacturing test development and deployment. You will support hardware development, test integration, test automation, and test deployment. You will work closely with cross-functional teams to ensure the optimal test coverage in production to ensure high-quality So Cs. You will have a strong understanding of Integrated Circuits (IC) flows, wafer processing, testing, qualification and failure analysis is expected. You will work with various groups to develop tests, automation methodologies, test program release, etc. You will also work on releasing cost effective production test solutions into mass production.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

The US base salary range for this full-time position is $138,000-$198,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Develop System Level Test (SLT) solutions for custom Application-Specific Integrated Circuits (ASIC) and SoC’s by specifying hardware and integration requirements, driving vendor interactions, developing software frameworks and test modules, and integrating test cases from silicon validation and system software and test teams.

• Partner with data center server and accelerator design teams to realize practical test solutions leveraging system design and test elements.

Minimum qualifications

• PhD degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.

• Academic, educational, internship, or project experience with product engineering, test engineering, hardware validation, silicon validation.

• Experience with Python programming or Linux/Unix.

Preferred qualifications

• Experience with SLT test flow development, test automation, and test deployment actively contributing to technical design and problem-solving.

• Experience implementing secure manufacturing solutions including provisioning, e Fuse and programming, life-cycle management, and SoC security.

• Familiarity with SLT test handlers from Advantest, Teradyne, Chroma, or others.