About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.).

• Perform Register-Transfer Level (RTL) coding (coding and debug in Verilog, System Verilog), function/performance simulation debug, and Lint/CDC/FV/UPF checks.

• Participate in synthesis, timing/power closure activities.

• Participate in test plan and coverage analysis of the block and SoC-level verification.

• Communicate and work with multi-disciplined and multi-site teams.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

• 8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or System Verilog.

• Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques.

• Experience with design sign-off and quality tools (e.g., Lint , CDC , etc.).

• Experience with SoC or IP architecture.

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

• Knowledge of high-performance and low-power design techniques, assertion-based formal verification, Field-programmable Gate Array (FPGA) and emulation platforms, and SoC architecture.

• Knowledge in one of the following areas such as Double Data Rate (DDR)/Low Power Double Data Rate (LPDDR), High-bandwidth memory (HBM).

• Excellent problem-solving and debugging skills.