• Develop and execute verification plans. Architect, develop and maintain verification test benches that support both random and directed testing.

• Participate in design, architecture and code reviews. Work with micro architects, architects and design teams and influence design decisions/feature intercepts.

• Lead performance validation for both pre-silicon and post-silicon. Work with emulation/FPGA prototyping teams in verifying system level use cases. Drive convergence of verification and coverage plans towards high quality and on-time tape-out. Drive methodology initiatives to improve efficiency and design quality.

• Lead or Manage a team of design verification engineers focusing on IP, Subsystem/SoC verification at unit, cluster, subsystem and full chip levels.

• Influence architectural feature level decisions with the understanding of workload performance. Adopt methodology improvements using AI and EDA capability to drive efficiency gains and innovation.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

• Bachelor's degree in Electrical Engineering or equivalent practical experience.

• 10 years of experience in the verification of IP designs such as IP, SoC, vector CPUs, etc.

• 8 years of experience with verification methodology such as Universal Verification Methodology (UVM).

• 4 years of experience in people management, developing employees.

• Experience with System Verilog, System Verilog Assertions (SVA) and functional coverage.