Use problem-solving and simulation techniques to ensure performance, power, and area (PPA) are within defined requirements.

Collaborate with cross-functional teams to debug failures or performance shortfalls and meet program goals in lab or simulation.

Design chips, chip-subsystems, or partitions within subsystems from synthesis through place and route, and sign off convergence, ensuring that the design meets the architecture goals of power, performance, and area.

Develop, validate, and improve Electronic Design Automation (EDA) methodology for a specialized sign off or implementation domain to enable cross-functional teams to build and deliver blocks that are correct by construction and ease convergence efforts.

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

5 years of experience with System on a Chip (SoC) cycles.

Experience with advanced design, including clock/voltage domain crossing, DFT, and low power designs.

Experience in high-performance, high-frequency, and low-power designs.