Own the planning, creation, and delivery of top-level floorplan deliverables and implementation for Silicon SOC projects from concept to working silicon volume.

Resolve structural or physical issues related to the integration of ASICs and So Cs, and collaborate with teams across Google to develop ideas for silicon and hardware projects.

Manage all cross-functional interactions related to top-level floorplanning of chip projects.

Develop and improve floorplan implementation methodologies. Support and execute implementation flows using both industry-standard and specialized internal tools.

Perform technical evaluations of vendors and IP, providing recommendations and assessments of process node trade-offs to meet PPA, and cost goals.

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

10 years of experience in physical design (e.g., with a focus on floorplanning, integration, or top-level chip assembly).

Experience in 3D Integrated Circuit (3D IC) design (e.g., multi-die partitioning, TSV planning, advanced chiplet and packaging technologies, optimizing PPA, and physical verification in a SiP context).

Experience in physical design working on advanced nodes.

Experience collaborating with cross-functional teams (e.g., architecture, RTL design, synthesis, verification).