Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios.

Create a constrained-random verification environment using System Verilog and the Universal Verification Methodology (UVM).

Identify and write all types of coverage measures for stimulus and corner-cases.

Debug tests with design engineers to deliver functionally correct design blocks.

Measure coverage to identify verification holes and to show progress towards tape-out.

Bachelor's degree in Electrical Engineering, Computer Science, or a related field, or equivalent practical experience.

1 year of experience with verification methodology (e.g., Universal verification methodology (UVM)).

1 year of experience in the verification of IP designs (e.g., IP, SoC, vector CPUs).

Experience with System Verilog, SVA, and functional coverage.