Perform Verilog/System Verilog Register-Transfer Level (RTL) coding, function/performance simulation debug and Lint/Clock Domain Crossing (CDC)/Formal Verification (FV)/Unified Power Format (UPF) checks.

Perform RTL verification using industry standard methodologies; participate in test planning and coverage analysis.

Develop RTL implementations that meet engaged power, performance and area goals.

Participate in synthesis, timing/power closure and Field-programmable Gate Array (FPGA)/silicon bring-up.

Create tools/scripts to automate tasks and track progress, while working with multi-disciplined and multi-site teams in RTL design, verification, or architecture/micro-architecture planning.

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

8 years of experience designing RTL digital logic using System Verilog for FPGA/Application-Specific Integrated Circuits (ASICs) or equivalent practical experience.

Experience with a scripting language such as Perl or Python.

Experience in area, power and performance.