About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will help build the Systems on Chip (So Cs) that power these data centers by developing and deploying test solutions with Automated Test Equipment (ATE) for high-volume manufacturing at wafer fabrication sites and outsourced semiconductor assembly and tests (OSATs). This is an opportunity to create silicon and follow it into the field to close the loop back to design and test for the next generation of chips. You will drive ATE manufacturing testing to validate performance and screen defective devices. You will own all aspects of ATE testing—including wafer sort, final test, and burn-in—and work with cross-functional teams to ensure optimal test coverage in production for high-quality So Cs.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Develop and implement strategies for manufacturing test of SoC products, including troubleshooting, test coverage optimization, defective parts per million (DPPM) reduction, and power and performance assurance.

• Participate in ATE test deployment and optimization for High Volume Manufacturing (HVM), working with the NPI product development and test team, vendors, and HVM product engineering.

• Collaborate with cross-functional teams globally, including ATE and SLT Test Engineering, Packaging, Supplier Management, and Operations, to build, deploy, and maintain an HVM screening solution.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.

• 2 years of experience in test engineering or product engineering.

• 2 years of experience with industry-standard tools, languages, and methodologies relevant to the development of silicon-based ICs and chips.

• Experience in ATE test development for New Product Introduction (NPI) or High Volume Manufacturing (HVM).

Preferred qualifications

• Master’s in Electrical Engineering, Computer Engineering, Computer Science, or related field.

• 8 years of experience in test engineering or product engineering.

• Experience with Scan/ATPG, Memory BIST (MBIST), or High-Speed I/O (HSIO) ATE testing, including ATE board and socket debugging.

• Knowledge of Automatic Test Equipment (ATE) platforms such as Advantest V93K or Teradyne Ultra Flex.