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About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will lead the development of custom mixed signal technology for Google’s consumer hardware. The analog mixed signal design team is a vertically integrated organization responsible for in-house design and development of IPs in Google’s consumer So Cs. These IPs span sensing, clocking, power management, high speed I/O (HSIO), and more. Our team owns architecture, schematic design, analog modeling, analog layout, RTL design, digital verification, digital physical design, sign-off, and integration support for our custom IPs. As analog and mixed signal design experts within Google, the team also serve as consultants for custom mixed-signal topics both within Google’s consumer hardware Silicon programs as well as the broader organization including Google and Alphabet partners.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
The US base salary range for this full-time position is $240,000-$334,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
Responsibilities
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Lead a team responsible for the design, verification, and implementation of analog and digital mixed signal IPs used inside Google’s consumer So Cs. Provide mentorship and managerial support.
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Drive development of Double Data Rate (DDR) and other HSIO interfaces from initial conception, through implementation to high-volume productization.
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Collaborate cross-functionally with peer groups in the broader organization to ensure that IP deliveries meet product Power, Performance, Area (PPA) and cost goals.
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Define and execute on a multi-year AMS roadmap for So Cs to help improve and differentiate Google products.
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Communicate and work with multi-disciplined and multi-site global teams.
Minimum qualifications
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Bachelor's degree in Electrical Engineering, a related field, or equivalent practical experience.
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15 years of experience with custom silicon design (So Cs, ASICs, etc.).
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5 years of experience in people management.
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Experience with both analog and digital mixed signal design (e.g., AMS, DMS) disciplines.
Preferred qualifications
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Master's degree or PhD in Electrical Engineering, or a related field.
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Experience with bleeding edge process nodes in silicon foundries.
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Experience leading cross-functional IP development and SoC integration.
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Experience with silicon engineering topics from architecture and implementation to productization and high volume manufacturing.
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Experience with High-Speed I/O (HSIO) PHYs, particularly DDR/LPDDR interfaces, with an understanding of the systemic issues related to power, performance, and thermal management in mobile and AI So Cs.
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Googleについて

Google specializes in internet-related services and products, including search, advertising, and software.
10,001+
従業員数
Mountain View
本社所在地
$1,700B
企業価値
レビュー
3.7
25件のレビュー
ワークライフバランス
3.8
報酬
4.2
企業文化
3.4
キャリア
3.9
経営陣
2.8
68%
友人に勧める
良い点
Excellent compensation and benefits
Smart and talented colleagues
Great perks and work flexibility
改善点
Management and leadership issues
Bureaucracy and slow processes
Constantly changing priorities and reorganizations
給与レンジ
57,502件のデータ
Junior/L3
L3
L4
L5
L6
L7
L8
Mid/L4
Principal/L7
Senior/L5
Staff/L6
Director
Junior/L3 · Data Scientist L3
0件のレポート
$176,704
年収総額
基本給
-
ストック
-
ボーナス
-
$150,298
$203,110
面接体験
9件の面接
難易度
3.4
/ 5
期間
14-28週間
内定率
44%
体験
ポジティブ 0%
普通 56%
ネガティブ 44%
面接プロセス
1
Application Review
2
Online Assessment/Technical Screen
3
Phone Screen
4
Onsite/Virtual Interviews
5
Team Matching
6
Offer
よくある質問
Coding/Algorithm
System Design
Behavioral/STAR
Technical Knowledge
Product Sense
ニュース&話題
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3d ago
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