Plan the verification of digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.

Create and enhance constrained-random verification environments using System Verilog and Universal Verification Methodology (UVM) or verify designs with System Verilog Assertions (SVA) and formal tools.

Debug tests with design engineers to deliver design blocks.

Close coverage measures to identify verification holes and to show progress towards tape-out.

Identify and write all types of coverage measures for stimulus and corner-cases.

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.

8 years of experience with verification methodologies and languages such as UVM and System Verilog.

Experience developing and maintaining verification test benches, test cases, and test environments.