About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a Power and Signal Integrity Engineer, you will be responsible for the design and characterization of signal and power integrity of our IC designs. You will design the external electrical interfaces of the device, from their Signal/Power-integrity and electrical usage perspectives and set up methodologies, perform simulations, silicon characterization and correlations to ensure our IC designs meet systems design budgets and achieve the highest performance. You will work with systems architects, ASIC design, systems engineers, and partner cross-functionally with teams and external vendors/partners.

The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

Responsibilities

• Generate precise electrical models (e.g., S-parameters, SPICE models) for components such as packages, PCBs, and connectors for use in simulations.

• Simulate high speed interface electrical behavior using HSPICE or other circuit simulators.

• Execute lab measurements utilizing test equipment like oscilloscopes, Vector Network Analyzers (VNA), Time Domain Reflectometers (TDR), spectrum analyzers to validate simulation outcomes and debug signal and power-related issues on silicon prototypes and boards.

• Establish design rules and guidelines for optimal signal/power integrity during PCB and package layout, ensuring high production yield and reliability.

• Document design specifications, analysis results, and validation reports to ensure compliance with standards and for future reference, while collaborating extensively with cross-functional teams, including ASIC architects, digital/analog designers, physical design/layout engineers, and system engineers.

Minimum qualifications

• PhD degree in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience.

• Experience in any signal and power integrity domain of electrical engineering through internships, academic research, or publications.

Preferred qualifications

• Experience with industry-standard Electronic Design Automation (EDA) tools for simulation and layout (e.g., Cadence Sigrity/Allegro, Ansys HFSS/PowerDC/Q3D, Keysight ADS, Synopsys HSPICE).

• Experience with signal and power integrity modeling and simulation for high-speed interfaces (e.g., LPDDR, MIPI, UFS, PCIe, USB).

• Experience with Ser Des testing in a lab setting, and familiarity with Ethernet, PCIE, and DDR standards.

• Experience in scripting languages such as Python, Perl, or Tcl for flow automation and data analysis.

• Familiarity with high-speed testing equipment like VNAs, TDRs, and oscilloscopes for measurement and validation.

• Knowledge of circuit analysis, electromagnetics, and transmission line theory.