About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As a Design Engineer, Custom Circuits and Static Random-Access Memorys (SRAMs) you will collaborate with circuit design, SRAM, physical design, technology, and architecture leads to deliver ASIC’s and SoC’s. You will work on topics that span circuit design, memories, digital block optimization, clock distribution, floorplanning, third-party IPs, and foundry engagement. You will manage products PPA by developing, optimizing, and integrating advanced SRAMs and other circuits..

You will conduct evaluations of custom SRAMs and drive selection of the optimal configurations and design architectures/features with foundry and vendor partner teams. You will supervise execution and deployment of the memories from inception to project integration and to tapeout. You will evaluate foundry process node PPA entitlement, identify product PPA bottlenecks, and drive new and novel circuit initiatives.

By co-optimizing across the entire design space, you will participate in the development of technology in high performance computing and define the next generation of datacenter-class silicon. By navigating the trade-offs in SRAMs and other critical circuits, you will ensure Google’s hardware achieves efficiency and power density.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

The US base salary range for this full-time position is $163,000-$237,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Evaluate, analyze, implement, and integrate SRAMs, other memories (such as multiport register files), and custom circuits. Drive proper IP integration and margins with the physical design team.

• Work with our foundry and IP partners plus our technology, physical design, and architecture teams in advanced CMOS nodes to optimize our products for Power Performance Area (PPA), schedule, and reliability.

• Drive and support test chip design, execution, and validation of critical circuit IPs.

• Design and build custom circuits at the transistor and gate levels to support physical design and power-performance-area optimization.

• Drive development of a leading edge technology platform for custom, high performance ASIC’s and SoC’s, from design through manufacturing, packaging, and test.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

• 5 years of experience in Circuit Design, Physical Design (RTL-to-GDS), or Technology Development, including advanced nodes (e.g., 7nm or below).

• Experience with custom circuit/IP and physical design, including Place and Route (PNR) and Static Timing Analysis (STA).

• Experience with SPICE and transistor level design in advanced nodes.

• Experience in CMOS device physics, finfet/GAA/nanosheet architectures, and layout parasitics.

• Experience in scripting and automation using Tcl and Python (or Perl).

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.

• 10 years of experience delivering optimized custom circuits, memories, IPs, and PNR blocks for product tapeout.

• Experience working with major foundry technology files (PDKs), standard cell libraries, metal stacks, and other features.

• Understanding of characterization and verification of standard cells/SRAMs/register files, including knowledge of power, noise, variation, and IR analysis.

• Understanding of collaterals for frontend and backend design teams.

• Strong documentation and presentation skills to communicate efficiently with teammates and vendors/partners.