About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a Senior Design Verification Engineer, you will be a part of Research and Development team to verify digital designs, develop constrained-random test environments and drive system testing to closure. You will collaborate with design and verification teams, manage the verification life-cycle and uncover bugs through corner-case testing.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Plan and execute the verification of digital design blocks by understanding specifications and working with design engineers to define key verification scenarios.

• Develop and refine random verification environments using System Verilog/UVM or Specman to ensure effective test coverage.

• Define and implement various coverage measures to capture stimulus and corner-case scenarios.

• Collaborate with design engineers to debug tests and ensure functional correctness of design blocks.

• Drive coverage analysis to identify verification gaps and demonstrate progress towards tape-out.

Minimum qualifications

• Bachelor's degree in Electrical Engineering or equivalent practical experience.

• 8 years of experience verifying digital logic at Register-Transfer Level (RTL) using System Verilog or Specman/E for Field Programmable Gate Arrays (FPGAs) or Application-specific integrated circuit (ASICs).

• Experience with Central Processing Unit (CPU ) implementation, assembly language, or compute System on a Chip (SOC).

• Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).

• Experience creating and using verification components and environments in standard verification methodology.

Preferred qualifications

• Master’s degree in Electrical Engineering or Computer Science.

• Experience with UVM, System Verilog, or other scripting languages (e.g., Python, Perl, Shell, Bash, etc.).