Plan and execute the verification of digital design blocks by understanding specifications and working with design engineers to define key verification scenarios.

Develop and refine random verification environments using System Verilog/UVM or Specman to ensure effective test coverage.

Define and implement various coverage measures to capture stimulus and corner-case scenarios.

Collaborate with design engineers to debug tests and ensure functional correctness of design blocks.

Drive coverage analysis to identify verification gaps and demonstrate progress towards tape-out.

Bachelor's degree in Electrical Engineering or equivalent practical experience.

8 years of experience verifying digital logic at Register-Transfer Level (RTL) using System Verilog or Specman/E for Field Programmable Gate Arrays (FPGAs) or Application-specific integrated circuit (ASICs).

Experience with Central Processing Unit (CPU ) implementation, assembly language, or compute System on a Chip (SOC).

Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).

Experience creating and using verification components and environments in standard verification methodology.