About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As a part of the Tensor Processing Unit (TPU) team, you will build machine learning accelerator ASICs for Google and positively impact Google’s products and billions of Google users across the globe.

In this role, you will be working in ASIC development, validation, software, tools, and methodologies. You will push the boundaries of chip-development and hardware/software integration and validation. You will lead cross-functional work streams focused on end-to-end hardware/software integration and validation to demonstrate system functionality and performance. You will help the Chip team meet development criteria and achieve production readiness in various validation environments and serve as a key bridge between design, verification, compiler, and performance teams, providing technical depth across the machine learning compute IP. You will write firmware, RTL, scripts, or test content to integrate and demonstrate subsystem and system functionality. You will validate this functionality on simulation, emulation, or post-silicon environments. You will support demonstrating and delivering that hardware and software systems are functional and performant. You will support the co-ordination, debug, and enablement of the platform.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving team behind Google's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

The US base salary range for this full-time position is $138,000-$198,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Review chip specification and design, develop the integration plan with software and system partners, co-ordinate hardware and software delivery and demonstrate functionality.

• Integrate and validate hardware and software designs, including first-party and third-party IPs, assist bringup of machine learning compute features, and develop firmware to help validate hardware functionality.

• Utilize hardware/software co-simulation methodologies leveraging Register-Transfer Level (RTL) simulation, Emulation, FPGA environments as appropriate, architectural simulators or performance models as required to correlate performance.

• Develop detailed test plans, based on design specifications coordinated with a cross-functional team (e.g., Design, Design Verification, Firmware, Compiler, Architecture).

• Assist debug discussions with Design, Design Verification, Architecture teams and help root-cause functional failures and performance issues through the product development cycle, while improving validation coverage and sign-off processes for high-quality tapeout and production deployment.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

• 2 years of experience in two or more of the following areas: computer architecture, embedded firmware, ASIC design or verification, integration and enablement of first-party or third-party IPs.

• Experience in hardware/software integration or validation.

• Experience with Register-Transfer Level (RTL) development, design verification, or evaluation.

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.

• Experience with C++/Python software design principles.

• Experience integrating hardware/software systems.

• Experience developing firmware for embedded systems or accelerators.

• Experience in debugging firmware using simulation tools.

• Knowledge of Real-Time Operating System (RTOS) internals.