Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.).

Perform Register-Transfer Level (RTL) coding (coding and debug in Verilog, System Verilog), function/performance simulation debug, and Lint/CDC/FV/UPF checks.

Participate in synthesis, timing/power closure activities.

Participate in test plan and coverage analysis of the block and SoC-level verification.

Communicate and work with multi-disciplined and multi-site teams.

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or System Verilog.

Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques.

Experience with design sign-off and quality tools (e.g., Lint , CDC , etc.).

Experience with SoC or IP architecture.