About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

In this role, you will architect the control-plane software for the entire high-speed Physical Layer (PHY). You will lead the development of complex state machines for link training and auto-negotiation that allow Google’s AI clusters to communicate reliably at next-generation data rates.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

The US base salary range for this full-time position is $192,000-$278,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Define the software architecture for multi-core embedded systems, manage memory maps, interrupt latency, and inter-processor communication (IPC).

• Lead the implementation of industry-standard link training and auto-negotiation protocols for high-speed ethernet and custom interconnects.

• Optimize firmware for time-to-link and power consumption, ensure the silicon stays within strict thermal envelopes during heavy AI training workloads.

• Act as the primary firmware interface for the RTL design team to define register maps, APIs, and hardware or software boundaries.

Minimum qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field.

• 10 years of industry experience in embedded firmware or digital signal processing (DSP) development.

• Experience with high-speed I/O (HSIO), high-bandwidth transceivers, or physical layer (PHY) control software.

• Experience in real-time operating systems (RTOS) and multi-threaded embedded programming.

Preferred qualifications

• Master's or PhD degree in Electrical Engineering, Computer Engineering, or a related technical field.

• Experience in pre-silicon emulation or firmware bring-up and validation.

• Experience leading the firmware delivery for a major silicon tape-out.

• Knowledge of ethernet (802.3) and PCIe protocol stacks and physical layer management.