About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

The US base salary range for this full-time position is $163,000-$237,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Perform Verilog/System Verilog Register-Transfer Level (RTL) coding, function/performance simulation debug and Lint/Clock Domain Crossing (CDC)/Formal Verification (FV)/Unified Power Format (UPF) checks.

• Perform RTL verification using industry standard methodologies; participate in test planning and coverage analysis.

• Develop RTL implementations that meet engaged power, performance and area goals.

• Participate in synthesis, timing/power closure and Field-programmable Gate Array (FPGA)/silicon bring-up.

• Create tools/scripts to automate tasks and track progress, while working with multi-disciplined and multi-site teams in RTL design, verification, or architecture/micro-architecture planning.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

• 8 years of experience designing RTL digital logic using System Verilog for FPGA/Application-Specific Integrated Circuits (ASICs) or equivalent practical experience.

• Experience with a scripting language such as Perl or Python.

• Experience in area, power and performance.

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.

• Experience implementing Graphics Processing Unit (GPU), Multimedia Intellectual Property (IP)(Camera, Display or COdec) or Machine Learning IP.

• Experience with ASIC design methodologies for clock domain checks and reset checks.

• Proficiency in scripting languages, C/C++ programming and software design skills.