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Senior ASIC RTL Engineer, Core IP

Google

Senior ASIC RTL Engineer, Core IP

Google

placeBengaluru, Karnataka, India

·

On-site

·

Full-time

·

1mo ago

Benefits & Perks

Professional development budget

401(k) matching

Generous paid time off and holidays

Comprehensive health, dental, and vision insurance

Competitive salary and equity package

Learning

Healthcare

Equity

Required Skills

Python

JavaScript

TypeScript

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.

Responsibilities

  • Perform Verilog/System Verilog Register-Transfer Level (RTL) coding, functional/performance simulation debug and Lint/Cyber Defense Center (CDC)/VCLP checks.

  • Participate in test planning and coverage analysis.

  • Develop RTL implementations that meet engaged power, performance and area goals.

  • Participate in synthesis, timing/power closure and support pre-silicon and post-silicon bring-up.

  • Work with multi-disciplined and multi-site teams in Architecture, RTL design, verification, Design for Test (DFT) and Physical Desig (PD).

Minimum qualifications

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

  • 8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or System Verilog.

  • Experience with ASIC design methodologies and QA flows (Lint, CDC, RDC, VCLP), defining design constraints (SDC) and Low-power intent (UPF).

Preferred qualifications

  • Master's or PhD degree in Electrical Engineering, Computer Engineering or Computer Science.

  • Experience with a scripting language like Perl or Python.

  • Experience in design and development of audio blocks or Mobile Industry Processor Interface (MIPI) display or camera sub-systems.

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About Google

Google

Google

Public

Google specializes in internet-related services and products, including search, advertising, and software.

10,001+

Employees

Mountain View

Headquarters

$1,700B

Valuation

Reviews

3.7

25 reviews

Work Life Balance

3.8

Compensation

4.2

Culture

3.4

Career

3.9

Management

2.8

68%

Recommend to a Friend

Pros

Excellent compensation and benefits

Smart and talented colleagues

Great perks and work flexibility

Cons

Management and leadership issues

Bureaucracy and slow processes

Constantly changing priorities and reorganizations

Salary Ranges

63,375 data points

Junior/L3

L3

L4

L5

L6

L7

L8

Mid/L4

Principal/L7

Senior/L5

Staff/L6

Director

Junior/L3 · Data Scientist L3

0 reports

$176,704

total / year

Base

-

Stock

-

Bonus

-

$150,298

$203,110

Interview Experience

9 interviews

Difficulty

3.4

/ 5

Duration

14-28 weeks

Offer Rate

44%

Experience

Positive 0%

Neutral 56%

Negative 44%

Interview Process

1

Application Review

2

Online Assessment/Technical Screen

3

Phone Screen

4

Onsite/Virtual Interviews

5

Team Matching

6

Offer

Common Questions

Coding/Algorithm

System Design

Behavioral/STAR

Technical Knowledge

Product Sense