Design and implement DSP algorithms for high-speed PHYs, focusing on FFE/DFE and timing recovery loops.

Perform rigorous fixed-point analysis to minimize bit-width (Area/Power) while maintaining the required Signal-to-Noise Ratio (SNR).

Develop bit-exact C++/SystemC models to verify RTL against architectural intent.

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.

10 years of industry experience in Digital Signal Processing (DSP) design or High-Speed Digital Logic design.

Experience implementing digital blocks for Communication Systems or PHY (Physical Layer) e.g., filters, interpolators, or timing recovery.

Experience in MATLAB, Python, or C++.