About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a CPU SoC DV Engineer, you will be responsible for ensuring the functional integrity of CPU subsystems from initial RTL simulation through to final silicon characterization. You will develop robust verification environments, drive Gate Level Simulations (GLS), and partner with ATE teams to debug and stabilize high-speed patterns in a production environment.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

The US base salary range for this full-time position is $138,000-$198,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Drive ARM SoC and sub-system level verification, simulation, and debug for CPU RTL and gate-level netlists.

• Lead post-silicon debug efforts to diagnose complex hardware failures and ensure pattern stability in production.

• Translate simulation-based functional sequences into ATE/SLT-ready formats, ensuring high-fidelity pattern conversion through virtual tester environments.

• Execute GLS and timing-annotated (SDF) simulations using industry-standard EDA tools.

• Generate and convert ATE patterns utilizing virtual tester environments to ensure high-fidelity translation from simulation.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.

• 4 years of experience with ARM-based SoC verification, including cache coherency, Network-on-Chip (NoC) interconnects, or high-speed bus protocols.

• Experience with post-silicon debug and diagnosing failures across Process, Voltage, and Temperature (PVT) corners.

• Experience in RTL verification and Gate Level Simulation (GLS) workflows.

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.

• Experience with UVM/OVM methodologies and using Python or Perl to automate ARM SoC verification flows.