About the job

Platforms Infrastructure Engineering team designs and builds the hardware and software technologies that power all of Google's services. Our computational tests are complex and unique, enabled by custom hardware designed and made in-house.

As a Senior Staff Signal Integrity Engineer, you will design and build the systems that are important to our largest and dynamic computing infrastructure. You will see those systems from concepts all the way through to high volume manufacturing. You will support the machinery that goes into our data centers affecting millions of Google users.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

The US base salary range for this full-time position is $221,000-$311,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Lead the development of SI simulation workflow for high speed serial link and low speed iOS by working with system Signal Integrity (SI) design team and cross-functional teams on data center hardware products.

• Be responsible for planning for the simulation tools to deliver against the product roadmap. Manage system interconnect bring-up and qualification, working with test engineers, including configuring chips to ensure adequate margin.

• Drive solutions for SI issues with design engineers, PCB designers, and the system team. Run trade-off analysis on performance and cost.

• Collaborate with board, chip, system engineers, design partners, and chip vendors to drive system SI design. Explore layout and manufacturing trade-offs, and ensure product functions as needed.

• Develop advanced modeling and automation methodology, and define signal integrity technology and roadmap for next generation product.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience.

• 8 years of experience working in a signal integrity technical environment.

• 5 years of experience in technical leadership.

Preferred qualifications

• PhD in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience.

• Experience with Allegro, MATLAB, PowerDC, PowerSI, High Frequency Structural Simulator (HFSS), and SIwave.

• Experience with the product development process for mass volume production design, with signal integrity and lab validation.

• Experience with Ser Des testing in a lab setting, with PCIE, DDR, SATA, and 100/200Gbps ethernet standards.

• Familiarity with PCB, connector, or cable design and assembly processes, including materials and component selection.

• Understanding of Serializer/Deserializer (SERDES) capabilities, and Forward Error Correction (FEC) and its implications for system design.