About the job

We are seeking a Silicon Pre-to-Post Validation Lead with experience in writing verilog code to join our team.

In this dual-capacity role, you will be responsible for both the silicon emulation (pre silicon) to silicon validation of Complementary Metal Oxide Semiconductor (CMOS) backplane. You will also be responsible for post silicon validation specification and execution. You will require an in-depth understanding of Register-Transfer Level (RTL) design, digital verification, and all aspects of micro display validation.
Google's Raxium display group has established a revolutionary semiconductor materials display technology that enables new functionality in display products, bringing to users a closer and more natural linkage between the digital and physical realms in applications such as augmented reality (AR) and light-field display. With start-up roots and a state-of-the-art compound semiconductor fab in Silicon Valley, Raxium is seeking to build upon its engineering team with an aim to disrupt next-generation display markets.

The US base salary range for this full-time position is $240,000-$334,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Provide support for RTL verification through the utilization of various emulation techniques and the development of corresponding design flows. Upon the arrival of the first silicon, lead the bring-up process on various debugging stations, including, but not limited to, Field-Programmable Gate Array (FPGA)-based platforms. Assist in the analysis of silicon failures and collaborate with design and test engineering teams to ascertain root causes.

• Advocate enhancements in the validation flow, encompassing new tools, methodologies, and scripts, to boost efficiency and coverage.

• Forge partnerships with the architecture, physical design, and test engineering teams to guarantee integration and execution of the Design-for-Test (DFT) plan.

• Architect, design, and implement digital logic utilizing verilog or system verilog, deriving from specifications.

• Work cross-functionally with the verification team to define test plans, formulate assertions, and debug logic issues, thereby ensuring functional correctness.

Minimum qualifications

• Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.

• 10 years of experience in analog circuit design, including simulation and verification.

• Experience working with relevant Electronic Design Automation (EDA) tools for circuit design and analysis.

Preferred qualifications

• 15 years of experience in Application-Specific Integrated Circuit/System on Chip (ASIC/SoC) design, with a focus on both digital logic design and Design for Testability (DFT) implementation.

• Experience with industry-standard EDA tools for synthesis, Static Timing Analysis (STA), and DFT.

• Experience with advanced DFT techniques such as hierarchical DFT, compression, and diagnosis.

• Proficiency in hardware description languages (Verilog, System Verilog).

• Excellent problem-solving, investigative, communication and teamwork skills.