
Organizing the world's information and making it universally accessible.
Chipset Power Architect, Silicon
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Lead the definition of power requirements for Tensor mobile So Cs to optimize Power-Performance-Area (PPA) under peak current and thermal constraints.
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Propose and drive power optimizations throughout the design process from concept to mass production.
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Define power KPIs and SoC/IP-level power targets, and lead cross-functional architecture, design, implementation and SW teams to achieve power targets in volume production.
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Model SoC and IP-level power and perform power rollups.
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Drive power-performance trade-off analysis for engineering reviews and product roadmap decisions. Represent the status of SoC power to the senior leadership team.
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Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
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10 years of experience in power management or low power design and methodology.
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Experience with full product delivery cycle (e.g., definition, architecture, design and implementation, testing, productization).
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关于Google

Google specializes in internet-related services and products, including search, advertising, and software.
10,001+
员工数
Mountain View
总部位置
$1,700B
企业估值
评价
10条评价
4.5
10条评价
工作生活平衡
3.2
薪酬
4.3
企业文化
4.1
职业发展
4.2
管理层
3.8
82%
推荐率
优点
Great benefits and perks
Innovative and interesting work
Career development and learning opportunities
缺点
High pressure and expectations
Long hours and heavy workload
Fast-paced and overwhelming environment
薪资范围
57,503个数据点
Mid/L4
Mid/L4 · Accessibility Analyst
1份报告
$214,500
年薪总额
基本工资
$165,000
股票
-
奖金
-
$214,500
$214,500
面试评价
9条评价
难度
3.4
/ 5
时长
14-28周
录用率
44%
体验
正面 0%
中性 56%
负面 44%
面试流程
1
Application Review
2
Online Assessment/Technical Screen
3
Phone Screen
4
Onsite/Virtual Interviews
5
Team Matching
6
Offer
常见问题
Coding/Algorithm
System Design
Behavioral/STAR
Technical Knowledge
Product Sense
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