
Organizing the world's information and making it universally accessible.
Chipset Power Architect, Silicon
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Lead the definition of power requirements for Tensor mobile So Cs to optimize Power-Performance-Area (PPA) under peak current and thermal constraints.
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Propose and drive power optimizations throughout the design process from concept to mass production.
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Define power KPIs and SoC/IP-level power targets, and lead cross-functional architecture, design, implementation and SW teams to achieve power targets in volume production.
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Model SoC and IP-level power and perform power rollups.
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Drive power-performance trade-off analysis for engineering reviews and product roadmap decisions. Represent the status of SoC power to the senior leadership team.
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Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
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10 years of experience in power management or low power design and methodology.
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Experience with full product delivery cycle (e.g., definition, architecture, design and implementation, testing, productization).
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Google 소개

Google specializes in internet-related services and products, including search, advertising, and software.
10,001+
직원 수
Mountain View
본사 위치
$1,700B
기업 가치
리뷰
10개 리뷰
4.5
10개 리뷰
워라밸
3.2
보상
4.3
문화
4.1
커리어
4.2
경영진
3.8
82%
지인 추천률
장점
Great benefits and perks
Innovative and interesting work
Career development and learning opportunities
단점
High pressure and expectations
Long hours and heavy workload
Fast-paced and overwhelming environment
연봉 정보
57,503개 데이터
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주식
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보너스
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$214,500
$214,500
면접 후기
후기 9개
난이도
3.4
/ 5
소요 기간
14-28주
합격률
44%
경험
긍정 0%