
Organizing the world's information and making it universally accessible.
Chipset Power Architect, Silicon
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Lead the definition of power requirements for Tensor mobile So Cs to optimize Power-Performance-Area (PPA) under peak current and thermal constraints.
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Propose and drive power optimizations throughout the design process from concept to mass production.
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Define power KPIs and SoC/IP-level power targets, and lead cross-functional architecture, design, implementation and SW teams to achieve power targets in volume production.
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Model SoC and IP-level power and perform power rollups.
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Drive power-performance trade-off analysis for engineering reviews and product roadmap decisions. Represent the status of SoC power to the senior leadership team.
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Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
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10 years of experience in power management or low power design and methodology.
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Experience with full product delivery cycle (e.g., definition, architecture, design and implementation, testing, productization).
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Googleについて

Google specializes in internet-related services and products, including search, advertising, and software.
10,001+
従業員数
Mountain View
本社所在地
$1,700B
企業価値
レビュー
10件のレビュー
4.5
10件のレビュー
ワークライフバランス
3.2
報酬
4.3
企業文化
4.1
キャリア
4.2
経営陣
3.8
82%
知人への推奨率
良い点
Great benefits and perks
Innovative and interesting work
Career development and learning opportunities
改善点
High pressure and expectations
Long hours and heavy workload
Fast-paced and overwhelming environment
給与レンジ
57,503件のデータ
Mid/L4
Mid/L4 · Accessibility Analyst
1件のレポート
$214,500
年収総額
基本給
$165,000
ストック
-
ボーナス
-
$214,500
$214,500
面接レビュー
レビュー9件
難易度
3.4
/ 5
期間
14-28週間
内定率
44%
体験
ポジティブ 0%
普通 56%
ネガティブ 44%
面接プロセス
1
Application Review
2
Online Assessment/Technical Screen
3
Phone Screen
4
Onsite/Virtual Interviews
5
Team Matching
6
Offer
よくある質問
Coding/Algorithm
System Design
Behavioral/STAR
Technical Knowledge
Product Sense
最新情報
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1w ago
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1w ago
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News
·
1w ago



