About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As the Design for Test (DFT) Engineer Lead, you will play a crucial role in DFT Architecture and DFT design, and support devices to production. You will be responsible for providing technical leadership in DFT, developing flows, automation, and methodology, planning DFT activities, tracking the DFT quality throughout the project life-cycle, and providing sign-off DFT to tapeout.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Lead and execute DFT activities in the design, implementation, and verification solutions for Application-Specific Integrated Circuits (ASIC).

• Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG).

• Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.

• Manage a DFT team planning, deliverables, and provide technical mentoring and guidance.

• Lead DFT execution of a silicon project, planning, execution, tracking, quality, and signoff.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.

• 8 years of experience in Design For Test from DFT architecture to post silicon production support.

• 4 years of experience with people management.

• Experience with DFT design and verification for multiple projects, DFT specification, definition, architecture, and insertion.

• Experience with DFT techniques and common industry tools, DFT and Physical Design flows, and DFT verification flow.

• Experience in leading DFT activities throughout the whole ASIC development flow.

Preferred qualifications

• Master's degree in Electrical Engineering or a related field.

• Experience in post-silicon Debug, test or product engineering.

• Experience in JTAG and iJTAG protocols and architectures.

• Experience in SoC cycles, silicon bring-up, and silicon debug activities.

• Knowledge of fault modeling techniques.