About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Contribute to DFT strategy and architecture (e.g., hierarchical DFT, Memory Built-In Self Test (MBIST), ATPG).

• Develop and drive DFT validation strategy for the SoC and Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic BIST, TAP controller, Clock Control block, and other DFT IP blocks.

• Integrate and connect MBIST logic including test collar around memories, MBIST controllers, e Fuse logic, and connect to core and TAP interfaces.

• Document DFT architecture, test sequences, and boot-up sequences associated with test pins.

• Execute Post Silicon ATE Bring up and sustenance and Lead complete DFT phase at wafer Level.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, a related field, or equivalent practical experience.

• 8 years of experience in DFT domain.

• 8 years of experience using electronic design automation (EDA) test tools (e.g., Spyglass, Tessent, Synopsys).

• Experience with ASIC DFT synthesis, STA, simulation, and verification flow.

• Experience working with ATE engineers (e.g., silicon bring-up, patterns generation, debug, validation on automatic test equipment, and debug of silicon issues, etc.).

Preferred qualifications

• Experience leading the DFT implementations.

• Experience in managing or mentoring the team technically.

• Experience with advanced technology nodes (5nm/3nm), 2.5D/3D-IC packaging, or high-speed I/O (Ser Des/DDR) testing methodologies.

• Experience managing global technical teams and driving vendor engagement.

• Ability to drive cross-functional timing closure, power analysis, and IR-drop mitigation for high-frequency designs.