About the job

As Head of Process Engineering, you will lead a multidisciplinary Process Engineering team to develop and scale a highly disruptive semiconductor display technology. You will be responsible for the fab process with all associated tools, and drive the strategic wafer fab roadmap to deliver key performance indicators and High Volume Manufacturing (HVM) yield capability.

Raxium is on the threshold of a transition into full-scale production, and so is seeking a leader that will foster a deep connection to LEAN quality principles and practice, and fortify a lasting culture of continuous improvement in a dynamic, high-growth environment. Importantly, beyond this core role, you will participate in guiding the overall strategy of Raxium (i.e., you will have a seat at the leadership table) as we look to grow and expand operations to meet projected demand.

Google's Raxium display group has established a revolutionary semiconductor materials display technology that enables new functionality in display products, bringing to users a closer and more natural linkage between the digital and physical realms in applications such as augmented reality (AR) and light-field display. With start-up roots and a state-of-the-art compound semiconductor fab in Silicon Valley, Raxium is seeking to build upon its engineering team with an aim to disrupt next-generation display markets.

The US base salary range for this full-time position is $237,000-$329,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Own the fab process engineering areas, ensuring seamless transitions from proof-of-concept, pilot to full-scale production. Includes lithography, wet chemistry, dry etch, thin film deposition, epitaxy, and other wafer process processes and modules.

• Guide the strategic wafer fab roadmap and deliver Key Performance Indicator (KPI) by overseeing process innovation, process automation, new tool installations and process capability enhancements.

• Utilize Statistical Process Control (SPC), Failure Mode and Effect Analysis (FMEA) and structured problem-solving (root cause analysis) to eliminate systemic bottlenecks and enhance lithography and etch module stability.

• Implement high volume wafer fab manufacturing best practice, equipment and process optimizations to maximize production efficiencies and optimize wafer output.

• Act as the technical liaison for fab operations, ensuring all safety, quality, and manufacturability standards are surpassed. Cultivate an engaged, process engineering team through proactive performance management and strategic development.

Minimum qualifications

• Master of Science in Electrical Engineering, Materials Science, Optics, Physics or related fields.

• 15 years of experience in semiconductor optoelectronics devices and semiconductor wafer fab manufacturing.

• 10 years of experience in engineering management within a semiconductor wafer fabrication environment, and team leadership during a product ramp from incubation.

• 5 years of expertise across multiple areas listed, such as lithography, etch, clean, thin film, polish, thermal, grind, hybrid bond, singulation, or compound semiconductor epitaxy.

Preferred qualifications

• Ph.D. in Electrical Engineering, Materials Science, Optics, Physics or related fields.

• Experience utilizing problem-solving, data query, and analysis, and a six sigma black belt certification.

• Experience in the process integration and yield improvement of optoelectronics devices.

• Experience in fab technical and operations oriented leadership defining the process robustness strategy and execution, self-starting in guiding engineering cross-functions, influencing executive stakeholders, and managing executive communication.