About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As a Silicon Product Test Engineer, you will be responsible for defining, implementing, and using the software, hardware, and analytics systems necessary to characterize and diagnose manufacturing test yield loss and in-field quality escapes for highly complex ASICs and So Cs

You will support silicon test strategy definition, and participate in creating design-for-test (DFT) and design-for-debug (DFD) specifications for complex So Cs in advanced technologies. As a member of the Silicon Engineering team, you will be directly responsible for planning, data analysis, diagnosing memory and logic scan test failures, increasing production quality, and enhancing yield.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

The US base salary range for this full-time position is $138,000-$198,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Develop and execute strategies for ASIC/SoC new product introduction, planning, bring-up, verification, characterization, and qualification support.

• Drive interactions with suppliers, wafer fabs, and OSATs. Own and drive checkpoints for key quality metrics.

• Audit screening programs before releasing to production.

• Setup and maintain test, diagnosis, and yield analysis infrastructure, including return material authorization (RMA) support.

• Collaborate with cross-functional teams across the globe including ATE test engineering, system level test, packaging, supply chain, and operations to ensure high production yield and high quality in-field operation.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Mechanical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture, or equivalent practical experience.

• 4 years of experience in product engineering, yield engineering, or test engineering.

• Experience in IC flows, wafer processing, advanced packaging, testing, and qualification.

• Experience with data analytics, yield improvement, and RMA handling.

• Experience in managing silicon NPI build schedules and material readiness, with a focus on product development requirements and samples milestones.

• Experience working with foundries and OSATs, and coordinating supply chains around the globe.

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Mechanical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.

• Experience with test industry standards, and DFT best practices, including automatic test pattern generation (ATPG) stuck-at fault/transition delay fault (SAF/TDF), high bandwidth memory (HBM), memory built-in self-test (MBIST), or repair, diagnostic tools, and yield improvement.

• Experience working with wafers fabs or advanced packaging for yield engineering.

• Experience delivering HVM screening solutions for high-performance computing chips in advanced technology nodes with low DPPM.

• Experience with statistical analysis (e.g., JMP) and yield management systems (e.g., Exensio, Yield Explorer).