About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

Google’s Silicon team is driving the future of cloud data center computing.

As a System on Chip Input Output (SoC IO) Architect, you will help define a new generation of Google’s products. You will have pivotal responsibilities and serve as the organization Mobile Industry Processor Interface (MIPI) focal point.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving team behind Google's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Evaluate different silicon solutions for executing MIPI and other IO peripheries: off-the-shelf components, vendor co-developments and custom designs.

• Drive vendor execution in various engagements: standard component, build to specification, and co-developments.

• Collaborate closely with software, design, verification, physical design, packaging, and silicon validation stakeholders to ensure that designs are complete, correct, and performant.

• Create high performance hardware/software interfaces.

• Collaborate in developing a new SoC.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.

• 15 years of experience working with mobile industry processor interface (C-PHY and D-PHY) architecture.

• 6 years of experience in people management and developing employees.

• Experience with system design principles for low latency, low power, throughput, security, and reliability.

• Cross-functional experience in micro-architecture, design, verification, logic synthesis, and timing closure.

• Experience with signal integrity and power integrity.

Preferred qualifications

• Master’s degree or PhD in Electrical Engineering or Computer Engineering.

• Experience with USB, Multi-Gigabit Ethernet (MGBE), PCIe and display port IPs.

• Experience with post-silicon bring-up and lab work.

• Familiarity with Gigabit Multimedia Serial Link (GMSL).