Create and support emulation models from Register-Transfer Level (RTL).

Drive system bring up on emulation platforms, debug test failures and simulation/emulation mismatches.

Bring up external Input/Output (I/O) interfaces (e.g., PCIe, Memories, SERDES, SPI, JTAG etc.) on the emulation platforms.

Develop and operate tests on the emulators and assist in bring-up processes from prototyping through post-silicon validation.

Contribute to ongoing methodology and automation improvements, constantly evolving and improving emulation efficiency and value.

Bachelor's degree in Electrical Engineering or a related field or equivalent practical experience.

2 years of industry experience with RTL design (e.g., Verilog or System Verilog) and simulation (e.g., VCS, Incisive or Questa).

Experience with coding or scripting in C, C++, Perl, TCL or Python.

Experience with emulation systems (e.g., Ze Bu, Palladium, Veloce), compilation, debugging, performance and methodology enhancements.