Lead the PCIe microarchitecture and RTL development, ensuring high-performance designs that strictly adhere to PPA targets, coding standards, and quality guidelines.

Manage the full RTL lifecycle, including documentation and coding, while ensuring the design is sign-off ready for Lint, CDC, and synthesis.

Partner with system architects to integrate the PCIe subsystem, ensuring it meets chip-level bandwidth, latency, and power consumption goals.

Coordinate with Verification and Physical Design teams to develop test plans, leverage PCIe VIP, and achieve successful timing closure.

Resolve complex protocol issues and lead post-silicon bring-up to ensure link integrity and subsystem performance.

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

5 years of experience in ASIC design, including one project focused on PCIe logic.

Experience debugging RTL using Verdi/VCS and automating tasks via Python or Perl.

Experience in System Verilog/Verilog for RTL development and microarchitecture definition.

Experience with PCIe protocol layers (e.g., Transaction, Data Link, and Physical) or LTSSM.

Experience with Clock Domain Crossing (CDC), timing closure, or synthesis flows.