About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Define and drive to the implementation of physical design Static Timing Analysis (STA) methodologies.

• Take ownership of STA of one or more physical design partitions and top level.

• Drive to the closure of timing and power consumption of the design.

• Contribute to design methodology, libraries, and code review.

• Define the physical design STA constraints rule sets for the Physical design engineers.

Minimum qualifications

• Bachelor’s degree in Electrical Engineering or equivalent practical experience.

• 5 years of experience with advanced design, including clock/voltage domain crossing, Design for Testing (DFT), and low power designs.

• 5 years of experience with Static Timing Analysis (STA) convergence on blocks, Subsystem (SS) or SoC.

• Experience with System on a Chip (SoC) cycles.

• Experience in high-performance, high-frequency, and low-power designs.

Preferred qualifications

• Master’s degree in Electrical Engineering.

• Experience in coding with System Verilog and scripting with Tool Command Language (TCL).

• Experience in VLSI design in SoC or experience with multiple-cycles of SoC in ASIC design.

• Experience in coding constraints and scripting with TCL.