About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As part of our Server Chip Design team, you will use the ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.

The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

Responsibilities

• Lead the Design Activities at IP’s, Sub Systems(S.S) and SoC.

• Plan, execute, track progress, assure quality, report status of the assigned activity.

• Lead a team of designers both directly and in teams.

• Define the Block/SoC level design documents such as Micro Architectural Specifications.

• Own IP, S, SoC strategies for clocks, resets, and debugs. Enforce global methodologies and drive enhancements.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.

• 8 years of experience in RTL Design cycle from IP to SoC and from specification to production.

• 8 years of experience in Technical leadership.

• Experience in the following areas: RTL Design, Design Quality checks, Physical Design aspects of RTL coding, and Power.

Preferred qualifications

• Experience with synthesis techniques to improve Register-Transfer Level (RTL) code, performance and power as well as low-power design techniques.

• Experience with Design For Test and its impact on Design and Physical Design.

• Experience with a scripting language like Python or Perl.

• Knowledge in one of these areas: PCIe, UCIe, DDR, AXI, CHI, Fabrics, and ARM processors.

• Knowledge of SOC architecture and assertion-based formal verification.

• Knowledge of high performance and low power design techniques.