Define, plan and execute end-to-end physical package substrate design of mobile SOC packages as a unique contributor, meeting performance/power/area requirements.

Manage and drive co-design initiatives across silicon, package, and system levels, including securing production sign-off for package designs.

Participate in the development of new silicon Internet Protocols (IPs) and packaging technology through system requirement analysis, feasibility studies and package test vehicle designs.

Collaborate closely with Signal integrity (SI)/Power Integrity (PI), Test, New Product Introduction (NPI) and Mechanical Engineering teams to refine and optimize product package architecture and design. Develop, implement and debug package design methodology and CAD flow.

Interface with packaging suppliers, ensuring package design and Bill of Materials (BOM) documentation meets requirements for high volume manufacturing.

Bachelor's degree in Mechanical, Material, Electrical Engineering, Technology, Science, a related field, or equivalent practical experience.

5 years of experience in chip package substrate design using Cadence APD (Allegro Package Designer) or Mentor Expedition with package tape-outs.

Experience in chip package substrate layout, design rules/verification, design for manufacturing (DFM) and taping out for production.

Experience in mobile SOC package design in the following technologies: FCCSP, Package on Package (PoP), InFO, RDL, IPD, 2.5D/3D, Chiplet.