Lead the definition of power requirements for Tensor mobile System-on-Chips (So Cs) to achieve Power-Performance-Area (PPA) with a primary focus on the memory subsystem (memory controller, DDRPHY, DRAM).

Own and drive cross-functional teams to deliver on power Key Performance Indicators (KPIs) for the memory subsystem and other major SoC IPs.

Propose and drive power optimizations for the memory subsystem throughout the design process from concept to mass productization.

Drive power-performance trade-off analysis for engineering reviews and product roadmap decisions.

Represent status of SoC power to the executive leadership team.

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.

10 years of experience with memory subsystem architectures, including for mobile So Cs.

Experience in power management or low power design/methodology, as well as with low power architecture and power optimization techniques.

Experience with full product delivery cycle (e.g., definition, architecture, design and implementation, testing, productization).