About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

In this role, you will own the development of flows, methodologies, and data management systems for physical design Electronic Design Automation (EDA) tools operating within the Google Compute Engine environment. You will survey industry trends, perform technical evaluations, and implement best practices to streamline Register-Transfer Level (RTL) to Global Distribution System (GDS) workflows, increasing the efficiency of our physical design engineers and ensuring the high quality of results for all ASIC tapeouts.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

The US base salary range for this full-time position is $163,000-$237,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Architect and implement next generation physical design EDA, and CAD tool workflows for ASIC development.

• Collaborate with chip design teams to implement tools and methodologies for physical design in leading edge process nodes.

• Develop auditing tools, checkers, and metric dashboards based on APIs from third-party EDA tools.

• Own the physical design of blocks and subsystems end-to-end.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

• 8 years of experience with physical design flow and methodologies.

• Experience with EDA tools for physical design (e.g., Cadence, Synopsys, Siemens).

• Experience in full-chip or block-level physical design.

• Experience with scripting in Python, Tcl, or Perl.

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.

• 10 years of experience in physical design flow and methodologies for high-performance ASIC/SoC projects.

• Experience in sign-off areas such as physical verification (Caliber/IC Validator), Formal Verification (LEC), extraction, low power verification, STA closure, and ECO flows.

• Experience in achieving optimal Power, Performance, Area (PPA) goals in complex designs.

• Familiarity with 2.5D/3D IC packaging and proficiency with advanced parasitic extraction tools (e.g., STARRC).

• Ability to develop and deploy repeatable design methodologies, focusing on low-power verification.