Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios.

Identify and write all types of coverage measures for stimulus and corner-cases.

Debug tests with design engineers to deliver functionally correct design blocks.

Measure to identify verification holes and to show progress towards tape-out.

Create a constrained-random verification environment using System Verilog and Universal Verification Methodology (UVM).

Bachelor's degree in Electrical Engineering or equivalent practical experience.

8 years of experience in Verification, verifying digital logic at RTL level using System Verilog or Specman/E for Field Programmable Gate Arrays (FPGAs) or ASICs.

Experience in verification and debug of IP/subsystem/So Cs in the Networking domain such as packet processing, bandwidth management, congestion control desired.

Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).